In recent years, electronic devices provided with an information communication function including a mobile terminal such as a mobile phone and an information communication terminal to be mounted on an automobile have their electronic parts made into one chip or more highly integrated in response to demands for reduction in scale and cost. In line with these situations, design has been made such that a plurality of tasks (programs) which operate on a CPU of an electronic device to realize various kinds of functions share a plurality of devices (e.g. DSP (Digital Signal Processor) or a memory).
Under these circumstances, in a case where a plurality of tasks use the same memory, for example, there possibly occurs a situation where one task exerts such an adverse effect on other task processing as disabling continuation of the processing.
Although with respect to, for example, communication between tasks operable on a plurality of CPUs such as a multi-core CPU or communication between tasks operable on a CPU and a DSP, perfunctory security is given by some security software, in a case where one memory is shared, there might occur a situation where one task destroys a memory region to be used by other task or where one task alters data on a memory processed by other task. In addition, the same situation might occur not only in a case of memory sharing but also in other device sharing.
Various control methods are proposed in order to prevent occurrence of the above-described problems in advance in the above-described case where a plurality of tasks (programs) use one device in common. In the following, the proposed control methods will be described with respect to literature.
Related art whose one example is recited in Patent Literature 1 (Japanese Patent Laying-Open No. 2002-342166) aims at improving security at the time of task change by enabling an access level to be changed only at the detection of an access to an address for a level change routine when an access level is changed and returning to a management program without fail after execution of the level change routine.
Related art whose one example is recited in Patent Literature 2 (Japanese Patent Laying-Open No. 2001-290691) discloses the system in which a secondary storage device registers a token that is generated in file open processing together with a file identifier of the opened file and notifies a user program of the registration, the user program records the notified token and file identifier in pair and transfers the paired token and file identifier when executing input/output processing on a file basis, and the secondary storage device which is asked to input/output on a file basis executes file input/output processing based on whether the designated pair of file identifier and token is registered or not. Such related art enables an unauthorized file access from a user program to be prevented while providing the user program with a file input/output function with low overhead without intermediary of an OS (Operation System).
Related art whose one example is recited in Patent Literature 3 (Japanese Patent Laying-Open No. 08-278953) discloses the system having a queue for sequentially queuing a computer discrimination number, a task number and a group number in an exclusive control request made from one of computers into each data region of each shared data device, a flag register in which a flag is set when none of the computers makes an exclusive control request on a basis of a data region of a shared data device, and a management table for automatically generating as many flag regions as the number of all the exclusive control requests having the same group number designated on a computer basis to set a flag of an exclusive control request allowed to access a data region, thereby executing simultaneous exclusive control access to a plurality of the data regions bridging over a plurality of shared data devices. Such related art enables loads on a computer or a shared data device related to an exclusive control request for accessing common resources in a decentralized processing system to be mitigated.
Japanese Patent Laying-Open No. 2002-342166.
Japanese Patent Laying-Open No. 2001-290691.
Japanese Patent Laying-Open No. 08-278953.
Among the control methods as related art, the related art recited in Patent Literature 1, in particular, has a problem because in order to find a task change, instruction fetch address coincidence is determined to sense call-up of specific processing (access level change routine) and allow access level change, there might occur a case where with an instruction cache, the access level change routine cannot be detected, and application to other master than a CPU is difficult because of lack of ordinary instruction fetch.
The related art recited in Patent Literature 2 also has the problems that modification (packaging of a token generation mechanism) is basically required on a target device side, that OS is used for the check in first open, that no access authorization continues over one open-close period of a target device and that no access authorization is assigned to other arbitrary master.
Furthermore, while the related art recited in Patent Literature 3 (Japanese Patent Laying-Open No. 08-278953) enables assignment of a task ID each time in a case of exclusive control, assigning a task ID at each target device access (e.g. read/write of memory) is hard to realize and impractical.